Ravine

RISC-V SIMT Engine

A pipelined multicore SIMT (Single Instruction, Multiple Threads) RISC-V architecture designed for parallel computing without architectural compromises.

Architecture Overview

Ravine implements a pipelined SIMT execution model with independent warp scheduling and implicit reconvergence. From the start, configurability was a focus. The hierarchical modular design theoretically allows scaling up to large core counts and wide SIMD paths. The choice of implementing SIMT with separate parallel hardware threads for each SIMT worker thread instead of RISCV-Vector-Extension vector lanes was made deliberately to reduce necessary vectorization complexity from compilers.

Key Features

• No Compromises: RISC-V binary compatible — no necessary custom instructions or modifications.
• Performance First: Pipelined architecture optimized for high throughput.
• Parallel Execution: multi-lane SIMT execution pipeline delivering massively parallel instruction processing.
• Independent Thread Scheduling: Each thread can be scheduled independently from thread group for maximal utilization and flexibility.
• Implicit Reconvergence: Automatic thread synchronization without explicit reconvergence points, simplifying the programming model.
• Scalable Design: Target design supports up to 80 cores.
• ML-Accelerated: A custom RISC-V extension for MX microscaling tiny-float operations is planned.

RISC-V ISA

Ravine implements the RISC-V ISA with multiple standard extensions for floating-point, atomic, and bit manipulation operations.

Base ISA

• RV32I: 32-bit RISC-V Base Integer Instruction Set

Standard Extensions

Extension	Description	Status
F	Single-precision floating-point	✅
A	Atomic instructions	❌
Zfinx	Floating-point values in integer registers	✅
Zba	Bit manipulation for address generation	✅*
Zbb	Basic bit manipulation	✅*
Zicond	Conditional operations	✅
Zicntr	Performance counters	✅
Zihpm	Hardware performance monitoring	❌
Zilsd	Load/store pair operations	❌

*: disabled by default

Combined ISA: RV32IZfinx_Zicond_Zicntr

Default System Configuration

• SIMT Width: 8 lanes per warp
• Warp Count: 16 warps (thread groups) per core
• Core Count: 1

Compliance

The current implementation is very much non-compliant. Ravine Version will stay at v0.1.x until full compliance with current RISC-V Instruction Set Manual is achieved. Only then version number will be bumped to v0.2.0.

currently missing features:

• Unprivileged ISA:
  • floats:
    • float rounding: specified rounding modes are ignored
    • subnormals: subnormal inputs and outputs of computation are flushed to zero.
    • div, sqrt: currently only approximations are implemented. A fully compliant scalar implementation is planned, where the approximate mode can be enabled programmatically.
    • nan, infinity: not fully implemented
    • fcsr: not implemented
  • fence: not implemented
• Machine-Level ISA:
  • trap handling

Roadmap

Ravine can be simulated with Verilator or synthesized with Yosys and Vivado. Vivado synthesis has successfully been tested on the Arty A7 35T FPGA development board. But beside the features missing for compliance, some other stuff is still planned:

TODO	Description
DDR3 RAM	connect with dev-board ram
true cache	associativity, victim cache, request buffer, etc
scratchpad	block-local memory

LLM

No AI/LLM generated code is present in this repository.